crnor
Condition Register NOR - 4C 00 00 42
crnor
Instruction Syntax
| Mnemonic | Format | Flags |
| crnor | crbD,crbA,crbB | - |
| crnot | crbD,crbA | Simplified (crbD,crbA,crbA) |
Instruction Encoding
0
1
0
0
1
1
D
D
D
D
D
A
A
A
A
A
B
B
B
B
B
0
0
0
0
1
0
0
0
1
0
0
| Field | Bits | Description |
| Primary Opcode | 0-5 | 010011 (0x13) |
| crbD | 6-10 | Condition Register bit Destination |
| crbA | 11-15 | Condition Register bit A |
| crbB | 16-20 | Condition Register bit B |
| XO | 21-30 | 0000100010 (34) |
| Reserved | 31 | 0 |
Operation
CR[crbD] ← ¬(CR[crbA] | CR[crbB])
The condition register NOR instruction performs a logical NOR operation between condition register bits crbA and crbB, and stores the result in condition register bit crbD. The result is 1 only when both input bits are 0, otherwise it is 0.
Note: When used with the same bit for both operands (crnot), this performs a logical NOT operation.
Affected Registers
Condition Register (CR)
(crbD bit only)
- CR[crbD] ← ¬(CR[crbA] | CR[crbB])
For more information on condition register operations see Section 2.1.3, "Condition Register," in the PowerPC Microprocessor Family: The Programming Environments manual.
Examples
Basic NOR Operation
# Test: neither condition is true cmpwi cr0, r3, 0 # Compare r3 with 0 cmpwi cr1, r4, 0 # Compare r4 with 0 crnor 2, 1, 5 # CR0[EQ] = ¬(CR0[GT] | CR1[GT]) beq neither_positive # Branch if neither is positive
Logical NOT Operation (crnot)
# Invert a condition register bit cmpwi cr0, r3, 0 # Compare r3 with 0 crnot 1, 2 # CR0[GT] = ¬CR0[EQ] (equivalent to crnor 1,2,2) bgt not_equal_zero # Branch if r3 != 0
All Conditions False Test
# Test that no error conditions are set lwz r3, error_flags(r0) andi. r4, r3, 0x01 # Test error bit 0 andi. r5, r3, 0x02 # Test error bit 1 crnor 2, 2, 6 # Check if neither error is set beq no_errors # Branch if no error conditions
Clear Condition Bit
# Clear a condition register bit (set to 0) crset 2 # First set CR0[EQ] = 1 crnot 2, 2 # Now clear CR0[EQ] = 0