crandc
Condition Register AND with Complement - 4C 00 01 02
crandc
Instruction Syntax
| Mnemonic | Format | Flags |
| crandc | crbD,crbA,crbB | - |
Instruction Encoding
0
1
0
0
1
1
D
D
D
D
D
A
A
A
A
A
B
B
B
B
B
0
0
1
0
0
0
0
0
1
0
0
| Field | Bits | Description |
| Primary Opcode | 0-5 | 010011 (0x13) |
| crbD | 6-10 | Condition Register bit Destination |
| crbA | 11-15 | Condition Register bit A |
| crbB | 16-20 | Condition Register bit B |
| XO | 21-30 | 0010000010 (130) |
| Reserved | 31 | 0 |
Operation
CR[crbD] ← CR[crbA] & ¬CR[crbB]
The condition register AND with complement instruction performs a logical AND operation between condition register bit crbA and the complement (NOT) of condition register bit crbB, and stores the result in condition register bit crbD.
Note: This instruction is useful for testing that one condition is true while another is false.
Affected Registers
Condition Register (CR)
(crbD bit only)
- CR[crbD] ← CR[crbA] & ¬CR[crbB]
For more information on condition register operations see Section 2.1.3, "Condition Register," in the PowerPC Microprocessor Family: The Programming Environments manual.
Examples
Basic AND with Complement
# Test: r3 > 0 AND r4 <= 100 cmpwi cr0, r3, 0 # Compare r3 with 0 cmpwi cr1, r4, 100 # Compare r4 with 100 crandc 2, 1, 5 # CR0[EQ] = CR0[GT] & ¬CR1[GT] beq valid_range # Branch if r3 > 0 AND r4 <= 100
Exclusive Condition Testing
# Test: first condition true AND second condition false cmpwi cr0, r3, 5 # Test r3 == 5 cmpwi cr1, r4, 0 # Test r4 == 0 crandc 2, 2, 6 # CR0[EQ] = CR0[EQ] & ¬CR1[EQ] beq exclusive_condition # Branch if r3==5 AND r4!=0
Error State Logic
# Valid operation: operation successful AND no overflow fcmpo cr0, f1, f2 # Floating-point compare crandc 2, 2, 3 # Valid = EQ & ¬SO beq operation_valid # Branch if equal and no summary overflow