Instruction Syntax

Mnemonic	Format	Flags
crnand	crbD,crbA,crbB	-

Instruction Encoding

Field	Bits	Description
Primary Opcode	0-5	010011 (0x13)
crbD	6-10	Condition Register bit Destination
crbA	11-15	Condition Register bit A
crbB	16-20	Condition Register bit B
XO	21-30	0111000010 (450)
Reserved	31	0

Operation

CR[crbD] ← ¬(CR[crbA] & CR[crbB])

The condition register NAND instruction performs a logical NAND operation between condition register bits crbA and crbB, and stores the result in condition register bit crbD. The result is 0 only when both input bits are 1, otherwise it is 1.

Note: NAND is equivalent to NOT(AND) - the complement of the AND operation.

Affected Registers

Condition Register (CR)

(crbD bit only)

• CR[crbD] ← ¬(CR[crbA] & CR[crbB])

For more information on condition register operations see Section 2.1.3, "Condition Register," in the PowerPC Microprocessor Family: The Programming Environments manual.

Examples

Basic NAND Operation

# Test: NOT(both conditions true)
cmpwi cr0, r3, 0       # Compare r3 with 0 
cmpwi cr1, r4, 0       # Compare r4 with 0
crnand 2, 1, 5         # CR0[EQ] = ¬(CR0[GT] & CR1[GT])
beq not_both_positive  # Branch if NOT(both positive)

Error Detection Logic

# Detect when not all operations succeeded
lwz r3, op1_result(r0) # Load first operation result
lwz r4, op2_result(r0) # Load second operation result
cmpwi cr0, r3, 1       # Check if first succeeded
cmpwi cr1, r4, 1       # Check if second succeeded
crnand 2, 2, 6         # Check if NOT(both succeeded)
beq handle_partial_failure # Handle case where not all succeeded

Exclusive Condition Testing

# Branch when at least one condition is false
fcmpo cr0, f1, f2      # Compare floating-point values
cmpwi cr1, r3, 0       # Compare integer
crnand 2, 2, 6         # NOT(both equal)
beq at_least_one_false # Branch if at least one comparison failed

Related Instructions

crand, crandc, creqv, crnor, cror, crorc, crxor